Conventional electronic design process proceeds sequentially through a schematic design stage to determine the schematic design of an electronic design, a physical design stage to construct the layout of the electronic design, and a verification stage at which various verification processes, such as design rule checking and physical verification, are performed to determine whether the electronic design complies with certain set of constraints, design rules, requirements, or goals (collectively constraints.) Nonetheless, any violations identified during the verification stage may require a costly and often time-consuming process to resolve such violations. For example, a layout designer may have to return to the physical design to move certain shapes or to reroute certain interconnects in order to satisfy a spacing constraint and re-submit the revised electronic design to the verification modules or design rule check engines to determine whether the revised electronic design satisfies the prescribed constraints or design rules. As a result, the electronic design process may involve an iterative process where designers loop among various stages of the process, hoping that the electronic design may be finally signed off for tapeout. In addition, a layout designer often does not know whether any portion of the layout violates certain constraints until the layout is complete and ready for verification. The advent of more complex design rules simply exacerbates the problems.
The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have exacerbated the issues in the physical design methodology process of electronic circuits. For example, most conventional electronic circuit design tools focus on post-layout verification of the power grid or interconnects when the entire chip design is complete and detailed information about the parasitics of the physical designs and the currents drawn by the transistors are known. In these conventional approaches, the conventional circuit synthesis step is followed by layout synthesis and each step is carried out independent of the other. This is again followed by a physical or formal verification step upon the completion of the entire physical layout to check whether the desired performance goals have been achieved after layout generation and extraction. These steps are carried out iteratively in the conventional approaches till the desired performance goals are met. Nonetheless, such an iterative approach wastes significant amount of resources because various physical design tools, such as the placement tool, the router, etc., and various schematic design tools, such as the schematic editor, the schematic level simulator(s), etc., are unaware of the electrical parasitics associated with the physical data of the design and the electrical characteristics associated with the electrical parasitics.
Thus, there exists a need for providing a method, a system, and an article of manufacture for implementing interactive, real-time checking or verification of constraints.